Semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. patent application Ser. No.12/659,185 filed Feb. 26, 2010, which is a Continuation of U.S. patentapplication Ser. No. 12/068,204 filed Feb. 4, 2008, which is aContinuation of U.S. patent application Ser. No. 11/637,714 filed Dec.13, 2006, which is a Continuation of U.S. patent application Ser. No.11/265,156 filed Nov. 3, 2005, which is a Continuation of U.S. patentapplication Ser. No. 10/860,011 filed Jun. 4, 2004, which is aContinuation of U.S. patent application Ser. No. 10/619,627 filed Jul.16, 2003, which is a Continuation of U.S. patent application Ser. No.10/350,084 filed Jan. 24, 2003, which is a Continuation of U.S. patentapplication Ser. No. 09/874,017 filed Jun. 6, 2001. Priority is claimedbased on U.S. patent application Ser. No. 12/659,185 filed Feb. 26,2010, which claims priority to U.S. patent application Ser. No.12/068,204 filed Feb. 4, 2008, which claims priority to U.S. patentapplication Ser. No. 11/637,714 filed Dec. 13, 2006, which claimspriority to U.S. patent application Ser. No. 11/265,156 filed Nov. 3,2005, which claims priority to U.S. patent application Ser. No.10/860,011 filed Jun. 4, 2004, which claims priority to U.S. patentapplication Ser. No. 10/619,627 filed Jul. 16, 2003, which claimspriority to U.S. patent application Ser. No. 10/350,084 filed Jan. 24,2003, which claims priority to U.S. patent application Ser. No.09/874,017 filed Jun. 6, 2001, which claims priority to Japanese PatentApplication Nos. 2001-119032 filed Apr. 18, 2001, and 2000-185908 filedJun. 16, 2000, the contents of which are hereby incorporated byreference into this application.

BACKGROUND OF THE INVENTION

1. Field of The Invention

The present invention relates to a semiconductor integrated circuitdevice, and, more particularly the present invention relates to asemiconductor integrated circuit device for use in fast and low poweroperation properties.

2. Description of the Background

As described in “Design Challengers of Technology Scaling” IEEE MICROvol. 19, No. 4, pp 23-29, 1999 (“document”) , the power consumption ofmicroprocessors and other such chips is increasing year after year. Inthe year 2000, some chips appeared on the market with a powerconsumption exceeding 100 W.

As described in document 1, the power consumption caused by a leakagecurrent also increases exponentially as the fabrication process producessmaller circuits. In particular, an increase in the subthreshold leakagecurrent has been noted. In addition to the subthreshold leakage current,junction leakage currents such as the gate channeling current and theGIDL (Gate-Induced Drain Leakage) current increase as the fabricationprocess produces smaller circuits as described in “Identifying defectsin deep-submicron CMOS ICs” IEEE Spectrum pp-66-71, September, 1996(“document 2”).

As described in document 1, power consumption Pac caused bycharging/discharging of a load among the power consumption types in theactive state of the above chip is proportional to the result of(operation frequency f) .times.(load capacity C).times.(supply voltageV).times.(supply voltage V). Typically, therefore, a low voltage hasbeen used as a supply voltage (hereafter, “conventional example 1”).

In order to reduce power consumption Psi caused by the sub-thresholdleakage current in the standby state of the. subject circuit,“Subthreshold-Current Reduction Circuits for Multi-Gigabit PRAMs”,Symposium on VLSI Circuits Digest of Technical Papers, pp 45-46, May1993 (“document 3”) proposes a power switch method. According to themethod, a power switch is disposed between a power line and a circuit,and the power switch is turned off when the circuit stands by(hereafter, “conventional example 2”).

In addition, “50% Active-Power Saving without Speed Degradation usingStandby Power Reduction (SPR) Circuit”, ISSCC Digest of TechnicalPapers, pp 318-319, 1995” (“document 4”) proposes a substrate biascontrol method. According to the method, the voltage of a substrateterminal of a MOS transistor of the subject circuit is switched betweenactive and standby states and the threshold voltage of the MOStransistor is switched between active and standby states, therebyreducing the subthreshold leakage current in the standby state(hereafter, “conventional example 3”).

Furthermore, “Suppression of Stand-by Tunnel Current in Ultra-Thin GateOxide MOSFETs by Dual Oxide Thickness MTCMOS (DOT-MTCMOS)”, ExtendedAbstract of the 1999 International Conference on Solid State Devices andMaterials, pp. 264-265, 1999 (“document 5”) describes a method forreducing power consumption pg 1 caused by the gate tunneling current inthe standby state. According to the method, a thick oxide PMOStransistor is disposed between a circuit configured by a thin oxide MOStransistor and a power line, and the power switch is thereafter turnedoff while the circuit stands by, thereby reducing the power consumptioncaused by the gate tunneling current in the standby state (hereafter,“conventional example 4”).

Alternatively, a method for managing chip level power consumption isdisclosed in the official gazette ,of JP-A-152945/1996. According tothis method, each function block requests a power management, apparatusfor a necessary power according to the load state, and the powermanagement apparatus calculates the total power consumption requestedfrom the function blocks. When the total requested power is within themaximum supply power available, the power management apparatus allowsthe requested power to be sent to the functional blocks. When the totalpower exceeds the maximum supply power, the power management apparatuscontrols the clock frequency and the supply voltage of each functionblock so that the total requested power does not exceed the maximumsupply power.

However, this disclosed method gives no consideration to the current inthe standby state, which is increasing as described above. Because thepower management apparatus cannot disable the operation of each functionblock, the integration of a circuit according to any of the methods inthe conventional examples has been limited. In addition, where the powermanagement apparatus controls the clock frequency and the supply voltageof each function block, the power consumption required for controllingthe apparatus itself is not taken into account. Thus, the power of achip to be controlled by the conventional methods has been limited.

Along with an increase in the number of functions required formicroprocessors or other such chips, the number of MOS transistorsintegrated on these chips, as well as their operational frequency, alsois increasing. Consequently, power consumption Pac caused by thecharging/discharging of the circuit load also increases. The method ofconventional example 1, when reducing this power consumption Pac, cannotcompletely address the incremental trend of the power consumption Pacbecause to keep or improve the operational speed of a chip in the stateof lowered supply voltage, where the Pac generally can be reduced,requires lower-setting of a threshold voltage for each MOS transistor ofthe chip or reducing the gate oxide thickness of the MOS transistor,causing both Ps1 and Pg1 to be increased exponentially. In spite ofthese problems, the method of conventional example 1 has typically beenconsidered the most effective for reducing the Pac value. The method hasthus been used widely as described in document 1.

Both Ps1 and Pg1 have also increased year after year as described indocuments 1 and 2. Although the methods of conventional examples 2through 4 are proposed to suppress an increase of Ps1 and Pg1, thosemethods can reduce neither the Ps1 nor the Pg1 while the chip is active.These methods can only reduce Ps1 and Pg1 while the chip stands by. Themethods in conventional examples 2 through 4 are effective only when thepower consumption values (Pg1 and Pg1) caused by the subthresholdleakage current and a gate channeling current can be ignored withrespect to the Pac value, since reduction of the Pg1 and the Pg1 is onlyrequired in the standby state in which the Pac becomes almost zero.Where both Pg1 and Pg1 are too large to be ignored with respect to thePac value, however, the Pg1 and the Pg1 may significantly affect thepower consumption of the chip in the active state. None of the methodsin the conventional examples 2 through 4 is therefore effective inreducing the power consumption.

SUMMARY OF THE INVENTION

The present invention, therefore, preferably provides a power controlcircuit that can manage and control both the active and standby modes ofeach circuit block of a chip. Because the power controlling of eachcircuit block by the power control circuit is accomplished prior to thewhole operation of the subject semiconductor integrated circuit, thepower consumption of the semiconductor integrated circuit can becontrolled properly. (In this point, the technique is different from theprior art disclosed in said JP-A-152945/1996, in which an amount ofpower to be supplied to each circuit block is controlled according tothe whole operation of a semiconductor integrated circuit.)

One preferred configuration of semiconductor integrated circuitaccording to the present invention includes a plurality of circuitblocks and a power control circuit, wherein each of these circuit blockshas a plurality of states, for example a first and a second state. Eachcircuit block works in accordance with its function in the first stateand rests in the second state. The power control circuit preferablydetermines the state of each of those circuit blocks so as not to exceedthe maximum power consumption of the semiconductor integrated circuit.

In accordance with at least one embodiment of the present invention, thepower control circuit gives consideration not only to the powerconsumption of each circuit block in each of a plurality of states, butalso to the power consumption by each state transition so as to decidethe state of each circuit block. At this time, the clock frequencysupplied to each circuit block and the leakage current of the circuitblock are controlled so as to vary the power consumption of each circuitblock.

This power control circuit enables its functions to be described by alanguage such as the HDL (Hardware Description Language) and may besupplied as electronic data distributed through a medium (e.g., anoptical recording medium such as a CD-ROM or a magnetic recording mediumsuch as a floppy disk) or through the Internet or an intranet. Use ofthis circuit block electronic data permits a semiconductor integratedcircuit to be advantageously designed under design properties of thepast or of third parties.

Where the specifications of an interface between a power control circuitfor controlling the Rower of each circuit block, as well as thespecifications of an interface between a power control module forcontrolling the power of each circuit block in the power control circuitand a power arbiter ARBIT for adjusting the power consumption among thesubcircuits are decided beforehand, the designer may be able to design asemiconductor integrated circuit more easily according to the presentinvention.

Additional objects, features and advantages of the invention will appearmore fully from the following detailed description, drawings andattached claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For the present invention to be clearly understood and readilypracticed, the present invention will be described in conjunction withthe following figures, wherein like reference characters designate thesame or similar elements, which figures are incorporated into andconstitute a part of the specification, wherein:

FIG. 1 is an embodiment of a chip of the present invention;

FIG. 2 is an embodiment of a power control method of the presentinvention;

FIG. 3 is an embodiment of a power table for states of subcircuits whenthe power control method of the present invention is employed;

FIG. 4 is an embodiment of a state transition graph of the states ofeach subcircuit;

FIG. 5 is an embodiment of subcircuit scheduling;

FIG. 6 is an embodiment of a chip of the present invention;

FIG. 7 is an embodiment of subcircuit scheduling;

FIG. 8 is the details of the embodiment shown in FIG. 1;

FIG. 9 is the details of a chip kernel CHPKNL shown in FIG. 1;

FIG. 10 is an embodiment of a design flowchart;

FIG. 11 is an embodiment of a chip that employs the power controlmethod-of the present invention;

FIG. 12 is a graph showing chip state transition with step by stepchanges of the Pmax value; and

FIG. 13 is a graph showing the dependency of the average powerconsumption (AVEP) and the execution time (EXET) of the chip of thepresent invention on the Pmax value.

DETAILED DESCRIPTION OF THE INVENTION

It is to be understood that the figures and descriptions of the presentinvention have been simplified to illustrate elements that are relevantfor a clear understanding of the present invention, while eliminating,for purposes of clarity, other elements that may be well known. Those ofordinary skill in the art will recognize that other elements aredesirable and/or required in order to implement the present invention.However, because such elements are well known in the art, and becausethey do not facilitate a better understanding of the present invention,a detailed description will be provided hereinbelow with reference tothe attached drawings.

First Exemplary Embodiment

FIG. 1 shows one presently preferred embodiment of a chip CHP1 thatemploys the power control method of the present invention. In FIG. 1,CKT1 to CKTn denote subcircuits. MCKT denotes a main circuit and CHPKNLdenotes a chip power manager (hereafter, “chip kernel”). DATS1 to DATSndenote data signals (data lines) and CTLS1 to CTLSn denote power controlsignals (power control lines). REOS1 to REQSn are request signals(request lines) and ACKS1 to ACKSn denote acknowledge signals(acknowledge lines). (Note: the same symbols are used for both signalsand lines for sending the signals.)

The main circuit MCKT accesses the subcircuits (CKT1 to CKTn) inaccordance with the following method to send/receive data via data linesDATS1 to DATSn, executing the functions that chip CHP1 is requested toperform. The main circuit MCKT is a circuit which is notpower-controlled and is privileged to access each of the subcircuitsCKT1 to CKTn. When the chip CHP1 is powered, the main circuit MCKT isactivated, and the subcircuits CKT1 to CKTn are activated as follows.Below, a description is made detailing how the main circuit MCKTactivates the subcircuit CKT1.

The main circuit MCKT is active and the subcircuits CKT1 to CKTn standby so as to minimize their power consumption just after the chip CHP1 ispowered. The standby state includes several different states such as theSTB and SLP states which are described with reference to FIG. 2 below.

Certain methods executed as follows may be used alone or in combinationto reduce power consumption. Some of these methods may include: (1) Noclock is supplied to the subcircuits CKT1 to CKTn; (2) No supply voltageis supplied; and (3) The leakage current is suppressed. These methodscan be combined according to the subject property as long as the chippower consumption is controlled within the maximum. For example, in thecase where the supply voltage is supplied to the subcircuits CKT1 toCKTn while the supply of the clock is stopped, each of the subcircuitsCKT1 to CKTn may be reactivated quickly by supplying the clock to it.Alternatively, when the methods (2) and (3) are combined, the staticpower consumption may be reduced more than when only the method (1) isused. The chip CHP1 can thus achieve power saving. When the subcircuitsCKT1 to CKTn stand by, the power control method can be varied amongthem; for example, only the clock supply may be stopped or both of theclock supply and the power-supply voltage supply may be stopped for eachsubcircuit separately.

When the main circuit MCKT intends to access the subcircuit CKT1, themain circuit MCKT issues a request signal REQ1 to the chip kernel CHPKNLso as to request access to the subcircuit CKT1. The chip kernel CHPKNLreturns an acknowledge signal ACKS1 to the main circuit MCKT to enablethe access, and the state of the subcircuit CKT1, when receiving a powercontrol signal CTLS1, makes a transition from standby to a state inwhich a normal operation of the subcircuit is enabled. The main circuitMCKT thus accesses the subcircuit CKT1 to send/receive data via the dataline DATS 1. The main circuit MCKT can continue to access the subcircuitCKT1 as long as the ACKS1 is valid. When the ACK1 is invalidated, themain circuit MCKT is preferably no longer able to access the subcircuitCKT1.

The chip kernel CHPKNL disables the main circuit MCKT from accessing(refuses access to) any subcircuit in the case where the preset maximumchip power Pmax is exceeded. At this time, upon receiving a request foraccessing a subcircuit from the main circuit MCKT, the chip kernelCHPKNL controls the state of each subcircuit to lower the powerconsumption under the Pmax value through the power control dines CTLS1to CTLSn, thereby enabling the main circuit MCKT to access the subjectsubcircuit. The chip kernel CHPKNL then issues an acknowledge signal(ACKS1 to ACKSn) to the main circuit MCKT, so that the main circuit MCKTcan access one of the subcircuits CKT1 to CKTn.

When the chip kernel rejects the request signal REQ1, the chip kernelCHPKNL communicates the rejection to the main circuit MCKT by ceasing tothe issue the acknowledge signal ACKS or by other means. The maincircuit MCKT may then decide whether to delay the access of thesubcircuit or cease accessing another subcircuit so as to access thefirst subcircuit. The chip kernel CHPKNL can also increase the margin ofthe power consumption of a standby subcircuit by reducing the leakagecurrent of the subcircuit.

A description is now made for an embodiment of a power control method(for generating a plurality of states—including standby states—withdifferent power consumption values) employed for subcircuits CKT1 toCKTn with use of power control signals CTLS1 to CTLSn. Thereafter, adescription is made for a state control method (hereafter, “subcircuitscheduling”) for controlling the state of each subcircuit so as to lowerthe chip power consumption under the preset maximum chip power Pmax,thereby enabling the main circuit MCKT to access a requested subcircuit.

FIG. 2 shows an embodiment of the power control method employed forsubcircuits CKT1 to CKTn. G1 through G3 denote AND gates, MP1 denotes aPMOS transistor, MN1 denotes an NMOS transistor, and MN2 denotes an NMOStransistor having a gate oxide tox2 thicker than the gate oxide tox1 ofMN1 and a threshold voltage (absolute value) Vth2 higher than thethreshold voltage (absolute value) Vth1 of the MN1. VDD and VSS denote apositive side power line and a negative (ground) side power linerespectively.

The thickness of a gate dielectric film is decided not only by aphysical length, but also by an electrical length. Consequently, MN1 andMN2 may be made of the same dielectric film material while the physicaldielectric film thickness is varied between them, or MN1 and MN2 may beequal in physical dielectric film thickness while the dielectricconstant is varied between the dielectric film materials used for them,or both dielectric film material and physical film thickness may bevaried between MN1 and MN2.

In FIG. 2, LG denotes a circuit for enabling the function of eachsubcircuit to be executed. In this embodiment, LG includes an inverterconfigured by a flip-flop FF, a PMOS transistor MP1, and an NMOStransistor MN1. The NMOS transistor MN2 is connected between the circuitLG and the negative side (ground) power line. The line connected to thedrain of the NMOS transistor is used as a virtual ground line WSS and anegative side (ground) power line of the circuit LG.

The power control signal (power control line) consists of CTLSa toCTLSc. When the first power control signal CTLSa is ‘H’, the NMOStransistor MN2 is on, and the circuit LG is thereby powered. When thefirst power control signal CTLSa is ‘L’, the NMOS transistor MN2 is off,and the power supply to the circuit LG is thereby stopped. When thesecond power control signal CTLB is ‘H’, a clock signal CLK is sent tothe GCLK via the AND gate G1, and a clock is thereby distributed intothe circuit LG. When the second power control signal CTLSb is ‘L’, theoutput GCLK of the AND gate G1 becomes ‘L’, and the clock distributioninto the circuit LG is stopped.

Hereinafter, the state of (CTLSa, CTLSb)=(‘H’, ‘H’) will be referred toas the ACT state, the state of (CTLSa, CTLSb)=(‘H’, ‘L’) will bereferred to as the STB state, and the state of (CTLSa, CTLSb)=(‘L’, ‘L’)will be referred to as the SLP state respectively.

In the ACT state, the circuit LG is powered. The chip CHP1, therefore,consumes the power due to the sub-threhold leakage current, the gatetunneling current, and others. In addition, because a clock isdistributed to the subcircuits, the chip CHP1 consumes the power due todischarging of the load. On the other hand, in the STB state, becausethe circuit LG is powered, the chip CHP1 consumes the power due to asubthreshold leakage current, a gate tunneling current, and others.However, because no clock is distributed to the subcircuits in the STBstate, the chip CHP1 does not consume any power which is otherwiseconsumed by discharging of the load. In the SLP state, because thecircuit LG is not powered, the chip CHP1 does not consume any powerwhich is otherwise consumed by a subthreshold leakage current, a gatetunneling current, and others. Because the MN2 has a high thresholdvoltage vth2 and a thick gate oxide tox2, no large gate tunnelingcurrent flows in the NMOS transistor MN2 that is off and nosub-threshold leakage current flows in the circuit LG via the NMOStransistor MN2. Naturally, because no clock is distributed to thecircuit LG, the chip CHP1 does not consume any power which is otherwiseconsumed by discharging of the load.

The third power control signal (line) CTLSc is connected to the ANDgates G2 and G3 to which the input signal IN and the output signal OUTof the circuit LG are connected respectively. When the CTLSc is ‘H’, thesignal IN entered from outside a subcircuit CKT is sent to the circuitLG via the AND gate G2 as a signal GIN. Also the output signal OUT fromthe circuit LG is output to the outside of the subcircuit CKT via theAND gate G3 as an output signal GOUT. On the other hand, when the thirdpower control signal CTLSc is ‘L’, the outputs from the AND gates G2 andG3 become ‘L’ respectively and the input signal IN from outside thesubcircuit CKT is not sent to the circuit LG. Therefore, the output GOUTfrom the subcircuit CKT remains ‘L’ regardless of the voltage value ofthe output signal OUT from the circuit LG.

Controlling the sending of the input signal by the AND gate G2 asdescribed above can thus prevent the signal GIN from unnecessary statetransition. For example, in the case where the third power controlsignal CTLSc is driven to ‘L’ while the circuit LG is in an inactivestate, such as the STB or SLP state in which no clock is distributedinto the circuit LG, the power consumption by unnecessary statetransition may be decreased. The output signal from the AND gate G3 canbe fixed so as to prevent an unstable voltage from being generated. Forexample, the voltage of the signal GOUT does not become ‘H’ nor ‘L’ inthe SLP state in which the circuit LG is not powered. It is alsopossible to prevent a short circuit current or other similar problemfrom occurring in the circuit that follows the circuit LG and thataccepts the signal GOUT. Consequently, although not specifically limitedthereto, the third power control signal CTLSc may be driven to ‘L’ inthe STB or SLP state so as to avoid the above problems effectively. Inthis case, the second and third power control signals CTLSb and CTLScmay be electrically tied together.

Where the high threshold and thick gate oxide NMOS transistor MN2 isused as a power switch as shown in FIG. 2, the power switch willpreferably have one or more of the following effects that are morepronounced than when a PMOS transistor is used as a power switch asdescribed in the document 5.

(1) When the power switch is on, the on-resistance must be lowered so asto reduce the impedance of the power supply. The NMOS transistor canobtain a smaller on-resistance than that of the PMOS transistor when thegate width is the same between them.

(2) A voltage higher than the VDDH can be applied to the gate of theNMOS transistor MN2 in the case where the NMOS transistor MN2 is on evenwhen the VDD is low. The NMOS transistor on-resistance can thus bereduced. In particular, when the NMOS transistor NM2 is configured by ahigh voltage tolerance MOS transistor, like a thick gate oxide MOStransistor used for an interface circuit (I/O circuit) with externaldevices of the chip CHP1, the fabrication process can be simplified. Inthis case, the VDDH can be set to the same voltage as that of the I/Ovoltage (VDDQ), whereby the VDDH generation circuit may be omitted.However, differences caused by the irregularity of fabrication could beallowable under the description of “the same transistor.”

FIG. 3 shows an example of the power consumption of each subcircuit whenthe power control method shown in FIG. 2 is employed. In this example, amicroprocessor CPU, a floating point unit FPU, a signal processor DSP,and a communication circuit RF are used as subcircuits. According to thescale and the property of each circuit, the power consumption is variedas shown in FIG. 3 among the three states (ACT, STB, and SLP). As shownin FIG. 3, the power consumption in the ACT state is the largest,followed by that in the STB state. In the SLP state, the power supply isshut off, thereby a negligible amount of power is consumed.

FIG. 4 shows an embodiment of a state transition diagram of thesubcircuit CKT including the three states of ACT, STB, and SLP. Anintermediate state preferably occurs at a state transition from SLP toSTB and at a state transition from STB to ACT as denoted by S1 and S2 inFIG. 4. With these intermediate states provided, each state transitionmay be executed stably.

For example, the circuit LG is powered in a state transition from SLP toSTB. Although it depends on the scale of the circuit LG, when thecircuit LG is powered, generally, a large rush current flows in thecircuit LG. This rush current is classified into some types, including acurrent caused by charging of the load in the circuit LG and a shortcircuit current caused in the charging process. Generally, a large shortcircuit current flows in the CMOS circuit when the input node voltage isneither the positive nor the negative (ground) side power-supply voltagepotentials. There exists a method for identifying this rush currentwherein the power is turned on gradually. Consequently, the gate signalof the MOS transistor MN2 is changed in level from ‘L’ to ‘H’ at a smallthrough-rate. The rush current, the power supply bump, and other effectscan thus preferably be reduced, and the whole chip may be prevented frommalfunctioning. This state transition is processed as a state S1. When astate transition is made to STB after completion of power supply to thecircuit LG is detected (T2), the whole chip can be prevented frommalfunctioning caused by an unstable power supply.

Where the gate signal of the NMOS transistor MN2 is changed in levelfrom ‘L’ to ‘H’ at a slow rate, completion of power supply to thecircuit LG can be detected by monitoring the MN2 gate signal potential.Consequently, the gate signal of the MOS transistor may only be requiredto be changed in level after the charging/discharging time of the nodein the circuit LG. This is because charging of the node in the circuitLG is completed when the gate signal of the MOS transistor MN2 ischanged in level to ‘H’ completely. In order to change the level of thegate signal of the MOS transistor MN2 after such time, it is onlyrequired that the gate of the MOS transistor is driven, for example, bya comparatively large output impedance driver. According to this method,the gate impedance of the MOS transistor MN2 increases. When it isexpected that this high impedance line is affected adversely by such anoise as a cross talk, the gate of the MOS transistor MN2 may be drivenagain by a comparatively small output impedance driver when thecompletion of the power supply to the circuit LG is detected in themonitoring of the MN2 gate signal potential.

FIG. 9 shows an example of a configuration to be used for this process(described below). The drivers C1, C2, and C3 in the buffer BUF arecircuits for executing the above driving method for the MOS transistorMN2. The driver C2 outputs a comparatively large impedance as describedabove. At first, the driver C2 is used to drive the MOS transistor MN2.The driver C1 outputs a comparatively small impedance and the circuit isused to monitor the MN2 gate signal potential.

The effect of the above state S1 is also obtained from the statetransition from STB to ACT. For example, in the case where apredetermined time is needed to distribute a clock signal, anintermediate state S2 may be set in the state transition from STB to ACTso as to absorb the predetermined distribution time.

Although not shown in FIG. 2, a decoupling capacitor should preferablybe connected between VDD and VSS. When the decoupling capacitor isconnected between VDD and WSS in this way, the noise removal performanceof the subcircuit is improved compared to when the decoupling capacitoris connected between VDD and VSS. In this case, however, the decouplingcapacitor is charged/discharged when the NMOS transistor MN2 is turnedon/off, whereby the power is consumed unnecessarily.

The connection method shown in FIG. 2 is not always used specificallyfor the terminals to which the MOS transistor substrate terminals areconnected. In addition, while the sub-threshold leakage current iscontrolled through the use of the power switching method that employsthe NMOS transistor MN2 in FIG. 2, the control method is not limitedonly to that; a substrate bias control method as described in document 4may also be used.

While it is assumed large circuit blocks such as a microprocessor CPU ora signal processor DSP are used as subcircuits LG in FIG. 3, the scaleof each of those subcircuits is not specifically limited to theseblocks. For example, one computing element and one memory circuit may behandled as a subcircuit respectively. A large-scale circuit ispreferably divided into many small-scale circuits for detailed powercontrolling.

Also, while three states are assumed in FIG. 3, there may be only twostates, such as SLP and ACT, or STB and ACT. There may also be four ormore states. The number of states may be set for each subcircuitindividually.

For example, only two states may be set for some subcircuits, while moreare used for others. The higher the number of states set, the more thepower may be controlled in detail.

The state transition method is not limited specifically to that shown inFIG. 4. An optimal state transition method may also be employed for eachchip or for each subcircuit.

FIG. 5 shows an exemplary embodiment of subcircuit scheduling. In orderto simplify the description, the state transition of each of thesubcircuits CKT1 to CKTn is done in accordance with the state transitionmethod shown in FIG. 4 so that the total power consumption of all thesubcircuits CKT1 to CKTn becomes 200 mW or less while the maximum powerconsumption Pmax of the chip is set to 250 mW. For example, the CKT1 isin the ACT state and both CKT2 and CKT4 are in the STB state at time 0.The total power consumption is 100 mW at this time. At time 1, a statetransition is done to ACT in the CKT2 and the power consumption isincreased to 150 mW. The state of each subcircuit is thus controlled soas to reduce the total power consumption under the Pmax.

As a specific method for subcircuit scheduling, there are manyemployable methods, for example, “UNIX Operating System ProcessScheduling” as described in “UNIX Kernel Design” Computer ScienceMagazine BIT separate volume by Maurice J. Bach (translated by AyaSakamoto), published by Kyoritsu Shuppan, p. 211.about.230, October,1990 (“document 6”), and “UNIX Operating System Memory Management” alsoin document 6, p. 231.about.263. The UNIX operating system executesprocess scheduling in accordance with the scheduling rules preset forevery process; swap-in and swap-out processings are executed for aplurality of processes on, the basis of memory limitation and executionlimitation. The memory limitation means an upper limit set for memorycapacity and the execution limitation means limitation of the number ofprocesses to be executed concurrently due to the limited number of CPUs.On the other hand, the chip of the present invention controls the powerconsumption of a plurality of subcircuits, so as to execute thescheduling rules defined for every subcircuit on the basis of an ideathat an upper limit is set for power consumption.

There are many methods for process scheduling and memory managementexecuted under the control of the UNIX operating system and each ofthose methods can apply to the subcircuit scheduling of the presentinvention. The method to be employed in this embodiment is not limitedspecifically to any one such scheme. For example, it is possible tocorrespond a state in which the UNIX operating system executes a processexisting in a memory (swap-in state) to the ACT state, a state in whichthe UNIX operating system stands by for execution of a process-existingin a memory (swap-in state) to the STB state, and a state in which thereis no process to be executed by the UNIX operating system in a memory(swap-out state) to the SLP state of the present invention respectively.

In addition to the UNIX operating system described above, there are manyother operating systems such as MICROSOFT WINDOWS. The processscheduling methods and the memory management methods used in thoseoperating systems can also be employed for the subcircuit scheduling ofthe present invention in the same way. In addition, there are many realtime operating systems such as uITRON. Those real time operating systemsare effective for special scheduling so as to assure the real timeproperty. Those real time operating systems can also apply to thesubcircuit scheduling of the present invention.

As described above, FIG. 5 shows an embodiment of subcircuit schedulingthat suppresses the total power consumption of the subcircuits CKT toCKTn under 200 mW in order to simplify the description. The powerconsumption caused by power state transition is also ignored in theembodiment shown in FIG. 7. In the case of the subcircuit scheduling ofthe present invention, however, while the state of a subcircuit iscontrolled so as to suppress the chip power consumption under the presetmaximum power consumption Pmax of the chip CHP1, the use of a requestedsubcircuit should be enabled. The power consumption by the statetransition of each subcircuit should preferably be taken intoconsideration. In particular, when a state transition causes the powersupply to be turned on/off, the power consumption by the statetransition itself often becomes so large that it cannot be ignored. Thisis because the power-off operation results in discharging of many nodesin the subject circuit and the power-on operation results in charging ofthose nodes in the circuit.

One of the methods for suppressing the overhead that may occur due tothe power consumption caused by many state transitions is to suppressthe state transition frequency. For example, the power supply may beturned off when no subcircuit has been accessed for a certain time. Inorder to achieve the processing, it may only be necessary to provide thechip with a circuit for limiting the state transition frequency of eachsubcircuit in the chip kernel CHPKNL or in each subcircuit CKT. In orderto achieve this, the information of the power consumption by the statetransition in each subcircuit is preferably stored and managed in eachsubcircuit CKT or in the chip kernel CHPKNL.

For example, each subcircuit CKT or the chip kernel CHPKNL may beprovided with an intermediate state (equivalent to the above powerconsumption information) in which the power consumption is reducedgradually (or kept at a fixed level) when the state of the subcircuit ischanged from ACT to SLP or from STB to SLP while the chip is powered.The number of such intermediate states should preferably be set higherwhen the power consumption caused by the state transition due to poweron/off and lower when the power consumption is small. For example, theintermediate states may be controlled as follows. When a subcircuitmakes a state transition from ACT to STB after the end of an operation,it is set so that the subcircuit passes the five intermediate states (S1to S5) sequentially before reaching the STB state, and the power supplyto the subcircuit is turned off when the subcircuit makes a statetransition from the intermediate state S5 to the STB state. Thetransition of those intermediate states is done at fixed cycles. In thiscase, when the state transition frequency is large, the subcircuitpreferably makes a state transition to the ACT state before it goes intothe STB state, that is, from an intermediate state (e.g., S3), therebythe large power consumption caused by the state transition can beprevented. It should be noted that when the power consumption by a statetransition can be ignored, the circuit for limiting the state transitionfrequency may be omitted.

Because the state transition frequency is controlled in this way, thepower consumption of the chip CHP1 including that caused by the statetransition of each subcircuit CKT is suppressed under a predeterminedvalue. The subcircuit scheduling should be controlled so as to minimizethe power consumption of the chip CHP1, preferably under the Pmax value,while consideration is given to the subcircuit scheduling so as to notonly suppress the power consumption of the chip CHP1 under the Pmaxvalue, but also to improve the processing performance of the chip CHP .

The method for limiting the power consumption of the chip CHP1 is notlimited only to those embodiments specifically described above. Wherethere are 10 subcircuits (CKT1 to CKT10) in the chip CHP1, thesubcircuit scheduling may be accomplished so as to suppress the totalpower consumption of the n (1.ltoreq.n.ltoreq.10) subcircuits among themunder a certain value. The subcircuit scheduling may also beaccomplished so as to suppress the total power consumption of thesubcircuits CKT1 to CKT3 and the total power consumption of thesubcircuits CKT4 to CKT10 under a certain value respectively. Any othermethods (e.g., any other subcombination of circuits) for limiting thetotal power consumption may be employed as long as the value issuppressed within the Pmax.

Various embodiments of the chip power controlling method of the presentinvention can preferably obtain one or more of the following effects:

(1) Because the chip CHP1 of the present invention can be controlled tosuppress the total power consumption thereof under the Pmax valueregardless of the chip circuit scale, it is possible to suppress anincrease of the power consumption Pac+Pg1 +Pg1 . When the powerconsumption Ps1 and/or others by a sub-threshold leakage current islarge, the conventional package of the chip has been confronted with arisk of thermal runaway. In particular, when the chip performs anasynchronous operation, the risk of thermal runaway increases. Thisoccurs because the chip's operational frequency increases due to a highheat. The present invention, however, may suppress the upper limit ofpower consumption, whereby it can prevent this thermal runaway.

(2) In the case of conventional chips, the maximum power consumptiontypically depends on the subject circuit scale and the operationalfrequency of the circuit. Therefore, the chip designer cannot know themaximum power consumption before beginning to design the circuit. Forthe chips of the present invention, however, the maximum powerconsumption of the subject chip can be decided by deciding the Pmaxvalue before designing the chip, whereby the designing process can besimplified.

(3) Where it is difficult to limit the power consumption of a chip, ithas been difficult conventionally to contract many designers who willdesign a subcircuit respectively so as to design one chip with use ofsubcircuits designed by those designers separately. This is because itis difficult to know the power consumption of each subcircuitbeforehand. For the chip CHP1 of the present invention, however, becausethe specifications of the chip kernel to be accessed via request linesREQ1 to REQn, acknowledge lines ACK1 to ACKn, and power control linesCTLS1 to CTLSn are unveiled so that each subcircuit is designedaccording to the specifications, even a highly integrated semiconductorIC can be designed more easily.

(4) In the case of conventional chips, it has heretofore been difficult,if not impossible, to integrate many low threshold voltage MOStransistors and/or many thin gate oxide MOS transistors on one singlechip due to the power limitation of the chip. For example, when 10million MOS transistors, each with threshold voltage of 0.2 V, areintegrated on one chip, 100 mA or more might be reached by thesub-threshold leakage current alone. When the power limitation is 100 mAor so, therefore, it has been impossible to integrate this many lowthreshold MOS transistors on one chip. For the chip of the presentinvention, however, the power consumption including the chip's leakagecurrent is controlled in accordance with the Pmax value, so it ispossible to integrate. 10 million of the above-described MOS transistorswith threshold voltages of 0.2 V on one single chip (hereafter, “virtualintegration”). However, when the Pmax value is small, it may beimpossible to power on and use all of those MOS transistorsconcurrently; when they are not used concurrently, no problem will arisefrom using all of those MOS transistors. In particular, when thethreshold voltage Vth1 of transistors that configure a subcircuit is 0.2V or less or when the gate oxide thickness tox1 is 4 nm or less, thesub-threshold leakage current and the gate tunneling current cannot beignored. The chip of the present invention is effective in this case.

(5) Because virtual integration is enabled for the chip of the presentinvention as described above, it is possible to set the thresholdvoltage Vthl of each MOS transistor used to execute the functions of thechip to a value lower than any of those of the conventional chips, aswell as to set the gate oxide thickness tox1 to a value lower than anyof those of the conventional chips. Consequently, the chip of thepresent invention may use many MOS transistors with higher performancecharacteristics (e.g., lower threshold voltage transistors) than any ofthe conventional chips, and the operational frequency of the chip can beset higher than any of the conventional ones. Because the presentinvention enables the chip kernel CHPKNL to limit the operation of eachsubcircuit to a certain level, the speed of the chip may be reduced.This problem can be solved, however, with use of higher performance MOStransistors than any of the conventional ones. The chip of the presentinvention can thus be expected to speed up the total performance of thechip in comparison to conventional chips.

Second Embodiment

In the first embodiment shown in FIG. 1, the main circuit MCKT accessesthe subcircuits CKT1 to CKTn under the control of the chip kernel.CHPKNL. In this second embodiment, any circuit privileged to access eachof the subcircuits CKT1 to CKTn can also be controlled for powerconsumption. FIG. 6 shows one example of this second embodiment.

CKT1 to CKT4 are subcircuits. The subcircuit CKT3 executes a functionwith use of the subcircuits CKT2 and CKT4. The subcircuit CKT3 executesa function with use of the subcircuits CKT2 and CKT4. The subcircuitCKT2 executes a function with use of the subcircuit CKT1. Therefore, thesubcircuit CKT3 is privileged to access the subcircuits CKT2 and CKT4,and the subcircuit CKT2 is privileged to access subcircuit CKT1. Eachsubcircuit is privileged under the control of the chip kernel CHPKNL asin the first embodiment shown in FIG. 1.

This second embodiment is preferably characterized as follows. Thesecond embodiment does not use the main circuit whose power consumptionis controlled by the chip kernel CHPKNL as shown in FIG. 1. Without themain circuit MCKT , however, a problem arises; in the case where all thesubcircuits are set in the SLP state shown in FIG. 3 when the chip ispowered, the chip is not activated. This is because no circuit isactivated (the chip cannot be activated forever). In order to avoid thisproblem, it is may just be required to preset a subcircuit (hereafter, a“boot circuit”) that goes into the ACT state, for example, when the chipis powered. In the configuration shown in FIG. 6, the subcircuit CKT3 ispreset as the boot circuit.

As shown in FIG. 6, there is none of request lines REQS and acknowledgelines ACKS provided for the boot circuit CKT3. After the chip ispowered, the boot circuit CKT3 is activated by the power control signalCTLS3. Being activated, the boot circuit CKT3 is privileged to accessthe subcircuits CKT2 and CKT4. The boot circuit activates thosesubcircuits as needed, thereby executing predetermined functions. Atthis time, the boot circuit CKT3 must be privileged by the chip kernelCHPKNL so as to access those subcircuits via the request line REQS andthe acknowledge line ACKS just like in the first embodiment. In the sameway, the subcircuit CKT2 accesses the subcircuit CKT1.

Where a privileged circuit (e.g., the subcircuit CKT3) is defined as ahost circuit and a circuit (e.g., the subcircuit CKT2 with respect tothe subcircuit CKT3) accessed by the host circuit is defined as a slavecircuit, then the boot circuit should be positioned at the highest level(that is, a subcircuit that has no subcircuits usable by itself) in thehierarchical order. In other words, the chip kernel CHPKNL cannotcontrol any circuit that cannot be accessed by the boot circuit directly(e.g., CKT2) or indirectly (e.g., CKT1).

The configurations shown in FIGS. 1 and 6, as well as the configurationsof the subcircuits CKT and the main circuit MCKT can be modified freely.For example, when the chip includes the main circuit MCKT in itsconfiguration, the subcircuits CKT may be configured hierarchically asshown in FIG. 6. There is no need to make a host circuit correspond toits slave circuits at the one-to-one relationship; the correspondencemay be one to many and many to one.

Third Embodiment

The physical and logical forms of the request lines REQS1 to REQSn, theacknowledge lines ACKS1 to ACKSn, the power control lines CTLS1 to CTLSnshown in FIGS. 1 and 6 are not specifically limited to those previouslydiscussed embodiments. In the configuration shown as a physical form inFIG. 2, each of the control lines CTLS1 to CTLSn consists of three linesCTLSa, CTLSb, and CTLSc. When power control signals are not transmittedin parallel as shown in FIG. 2, but are transmitted serially, only onepower control line may be used for power controlling. Of course, in thecase where the types of power controlling are limited, the number oflines can be reduced.

This same configuration holds true for the request lines REQS1 to REQSn.Where there is only one type of state transition (e.g., only ACT and STBare used), a single-bit request signal can be sent by one request line.Where there are more than three states and there are a plurality ofstates to be set as shown in the embodiment in FIG. 4, a plurality oflines may be used to send a request signal consisting of 2 or more bitsfor requesting a transition to each state. When a transition to each ofthose states is requested, priority should preferably be given to thetransition. The state transition of the power of each subcircuit forsubcircuit scheduling is thus controlled according to the priority. Thechip kernel CHPKNL enables a higher priority request to access thetarget subcircuit, thereby improving the access efficiency of thesubject resource.

The request lines REQS1 to REQSn, the acknowledge lines ACKS1 to ACKSn,and the power control lines CTLS1 to CTLSn may be bundled into a bus(hereafter, “power control bus”) and connected to each subcircuit. Wherethere are many subcircuits, the wiring area of the lines can be reduced.In addition, the bus will make it easy to extend the chip. In such acase, the bus is preferably structured so as to avoid a conflictoccurring among a plurality of accesses to the single bus. Because therequest signal REQS is output from each subcircuit at a given timing,the common bus cannot be shared by the request lines REQS1 to REQSn.Where the round-robin method or the token ring method is employed,however, the request signal REOS may be delayed in reaching somesubcircuits. The expandability of the chip, when in designing, willpreferably more than make up for this deficiency. It is also possible tocollect the acknowledge line ACKS and the power control line CTLS into acommon bus while the request lines REQS may be connected to thesubcircuits by the point-to-point method. In this case, the requestsignal from each circuit reaches the chip kernel fast and equally.

It is possible to use an on-chip bus provided in a conventional chip soas to transfer signals (e.g., Advanced Microcontroller Bus Architecture(SMBA) of ARM Corporation, Britain), as well as some or all of thesignal lines may be used commonly as a power control bus.

Fourth Embodiment

The maximum chip power consumption Pmax may be determined when thesubject chip is fabricated and/or designed so as never to be changedlater. The Pmax may alternatively be changed after the chip isfabricated. In order to enable the Pmax to be changed later, the Pmaxmay be stored in a non-volatile memory integrated on the chip. The Pmaxmay also be read from an external source when the chip is powered. ThePmax may also be determined in accordance with the specifications of thewire bonding of the chip and/or by means of jumper switching with use ofmetal formed on the chip. There are also various other methods fordeciding the Pmax, and those methods are not limited specifically tothose methods disclosed here.

Where the maximum chip power Pmax is set so as to be changed after thechip is designed, the Pmax can be varied among packages even when thesame circuits are integrated on their chips in those packages.Generally, in the case where a low-priced plastic package is used forthe chip, the maximum allowable power consumption of the chip decreases.This is because the plastic package is large in thermal resistance andlow in resistance to heat. In such a case, the Pmax value may be reducedto compensate for this. On the contrary, in the case where a high-pricedceramic package is used for the chip, the Pmax value can be increased.The higher the Pmax value is set, the more subcircuits that can bedriven concurrently. The chip performance may thus be improved. When thePmax is varied among packages, the chip performance can be set freelyfor each package.

Where the Pmax value is varied among package types in this way, circuitdesigning can be done commonly for both fast version chips and low powerconsumption version chips so as to lower the development cost and makeit easier to provide many types of low cost chips.

FIG. 7 shows an embodiment of subcircuit scheduling that is differentfrom that shown in FIG. 5. In the subcircuit scheduling shown in FIG. 7,the Pmax value is set lower than that shown in FIG. 5 and the totalpower consumption of the subcircuits is set to 150 mW. In FIG. 5, thetotal power consumption of the subcircuits at time 5 is 200 mW. In FIG.7, however, the state transition from CKT1 and CKT4 to ACT is delayedrespectively, whereby the total power consumption of the subcircuits isreduced to 150 mW or less. For example, in the case where the subcircuitscheduling shown in FIG. 5 is defined as subcircuit scheduling for fastversion chips, that shown in FIG. 7 will become subcircuit schedulingfor low power consumption version chips. In this way, the presentinvention can vary the Pmax value among specifications of chips thatrequire a balance between processing performance and power consumption.

The possibility of Pmax value changes after the chip is designed meansthat the Pmax can be changed even after the chip is re-fabricated in adifferent fabrication process. The Pmax can be set optimally in eachfabrication process.

Furthermore, the maximum power consumption Pmax of a chip may also bechanged after the chip is powered. For example, the Pmax value may bechanged according to the temperature of the chip. When the chiptemperature rises, the Pmax value decreases. When the chip temperaturedrops, the Pmax value increases. Because there is a relationship betweenchip temperature and power consumption (Tj=Ta+.theta..times.W, whereinTj: junction temperature, Ta: peripheral temperature, .theta.: packagethermal resistivity, W: power consumption) while the relationshipincludes a time lug, the present invention can manage chip temperatures.

Where a battery is used to drive the chip of the present invention, thePmax value may be changed according to the residual level of thebattery. When the residual level is still high or when the power to thechip is supplied from an AC outlet, the Pmax increases. When theresidual level goes down, the Pmax decreases. When the power from the ACoutlet is shut off, the Pmax may be reduced. Then, the battery drivingtime may be extended.

Fifth Embodiment

In order to take the power consumption of each subcircuit intoconsideration when in subcircuit scheduling, the chip kernel CHPKNL isrequired to know the power consumption in each state of each subcircuitas shown in FIG. 3. There are many methods for knowing the powerconsumption. The present invention enables any of those methods to beemployed. For example, a table as shown in FIG. 3 may be stored in thechip kernel CHPKNL when the subject chip is designed. The powerconsumption in each state may be stored in each subcircuit so that thechip kernel CHPKNL reads the information therefrom according to aspecific protocol, for example, when the chip is powered.

Sixth Embodiment

Subcircuit scheduling should be done by privileging the main circuitMCKT to access a target subcircuit via an acknowledge line ACKS as earlyas possible after the chip kernel CHPKNL receives the request via arequest line REQS. This is to improve the processing performance of thechip. One of the methods for the subcircuit scheduling is to avoid statetransitions that take much time in the subcircuit scheduling as often aspossible. For example, in the state transition graph shown in FIG. 4,state transition to SLP should preferably be avoided in scheduling. Thisis because the state transition from SLP to ACT or STB causes a power-onoperation and takes more time than the state transition from STB to ACTthat does not cause any power-on operation. In order to realize thesubcircuit scheduling, the number of intermediate states via which statetransition from ACT (or STB) to SLP must be increased higher than thenumber of intermediate states via which state transition from ACT to STBis accomplished. For a method that does not use the SLP state, however,the power reduction effect decreases. This may present a problem.

The main circuit MCKT may request the chip kernel CHPKNL to makesubcircuit scheduling for accessing a subcircuit before the actualaccess time, thereby reducing more power consumption. When receivingsuch a request, the chip kernel CHPKNL makes subcircuit scheduling forenabling the main circuit MCKT to access the target subcircuit as soonas possible upon acceptance of the next request for the actual access.This subcircuit scheduling preferably makes it possible to reduce thetime required between receiving a scheduled access request and enablingthe actual access, whereby the processing performance of the chip may beimproved. For example, the main circuit MCKT requests a scheduled use ofa subcircuit so as to execute the function and transfer the state of thesubcircuit from SLP to STB in advance. When the main circuit MCKTreaches the actual access time, the main circuit MCKT makes a request tobe privileged to access the subcircuit, whereby a state transitionoccurs from STB to ACT in the subcircuit. The main circuit MCKT can thusaccess the subcircuit more quickly after the actual access request isissued.

Seventh Embodiment

In FIG. 2, the NMOS transistor MN2 (power switch) is used to control thesub-threshold leakage current. The circuit configuration for reducingpower consumption is not specifically limited to that shown in FIG. 2. Apower supply circuit may be incorporated in the semiconductor integratedcircuit device, whereby the supply voltage is changed. As describedabove, because the power consumption required when the CMOS circuit isactive is proportional to the square of the supply voltage, the power ofthe circuit LG can be controlled with at least two states provided so asto be activated by a low supply voltage (e.g., 0.5 V) and a high supplyvoltage (e.g., 1.2 V).

In the embodiment shown in FIG. 2, when the MOS transistor MN2 is turnedoff, the information stored in such an information storage element suchas a flip-flop in the circuit LG is erased. One of the methods thatpreferably prevents such a problem is to provide the subjectsemiconductor IC device with a level holder circuit that can retain theinformation even when the MOS transistor MN2 is turned off. For example,this level holder circuit works between a positive power line VDD and anegative (ground) power line VSS. It can be realized as a latchingcircuit configured by transistor driven by a comparatively low power.Where the semiconductor IC device is provided with, at least two statesto be activated by a low supply voltage and a high supply voltage, bothbeing supply voltages of a subcircuit as described above, the supplyvoltage to be applied to the subject subcircuit with the low supplyvoltage is set so as to erase the information stored in the storageelement (flip-flop) in the subcircuit (it is avoided to set a low supplyvoltage that fails in keeping the information here). In such aconfiguration, the level holder circuit described above may be omitted.Such a voltage can speed up the state transition to the high supplyvoltage state and the power consumption required for the statetransition may be reduced.

In FIG. 2, the AND gate G1 is used to control (on/off) the clock sent tothe circuit LG. In other words, the control method shown in FIG. 2 isaccomplished by switching the clock between predetermined frequencyclock oscillation and 0 frequency clock oscillation on the other hand,the AND gate G1 may be replaced with means for changing the clock CLKfrequency (e.g., a divider or a phase locked loop (PLL) circuit). Asdescribed above, because the power consumption, when the CMOS circuit isactive, is proportional to the operational frequency, the power of thecircuit LG can be controlled with at least two states to be activated bya low operational frequency (e.g., 10 MHz) and a high operationalfrequency (e.g., 200 MHz).

FIG. 8 shows a configuration of a subcircuit enabled to realize such avariety of power control methods. While the FIG. 8 configuration isbased on FIG. 1, the subcircuit configuration also parallels that shownin FIG. 6. The subcircuits CKT1/CKT2 are configured by power controlcircuits PWC1/PWC2, circuits LG1/LG2 for realizing the function of thesubject subcircuit, and interface circuits IFC1/IFC2 used to communicatewith an external device.

The power control circuit PWC controls the power consumption caused bycharging/discharging of the load of the subcircuit and the powerconsumption caused by a leakage current according to the commandreceived from the chip kernel CHPKNL via a power control line CTLS.Clock frequency variable circuits such as a power supply circuit or aPLL circuit are concrete configuration examples of the power controlcircuit PWS.

Where the supply voltage supplied to each circuit LG as described aboveis varied among the subcircuits so as to control the power consumption,it requires an interface circuit between those subcircuits or betweeneach subcircuit and the main circuit MCKT. This is to prevent a leakagecurrent such as a short circuit current to flow in CMOS circuits withdifferent supply voltages when they are connected to the interfacecircuit. Use of an interface circuit IFC may prevent such a shortcircuit current. The official gazette of JP-A-195975/1999 discloses aconfiguration of a level converter circuit preferred for the interfacecircuit IFC to which subcircuits with different supply voltages areconnected.

The correspondence between the configurations shown in FIGS. 2 and 8 isdescribed below. The AND gates G2 and G3 are equivalent to the interfacecircuit IFC respectively and the NMOS transistor NM2 and the AND gate G1are equivalent to the power control circuit PWC respectively.

Ninth Embodiment

FIG. 9 shows one presently preferred embodiment of a configuration ofthe chip kernel CHPKNL. Buffers BUF1 to BUFn are circuits for drivingthe power control lines CTLS. Sequencers SEQ1 to SEOn are used to makestate transitions as shown in FIG. 4. The power table PWRTAB storespower values in various states as shown in FIG. 3, as well as powervalues (or energy values) required for state transitions. The drivers C1to C3 of the buffers BUF1 to BUFn were described with respect to thefirst embodiment. Each of the power control modules PCM1 to PCMn isconfigured by a sequencer (SEQ1 to SEQn) and a buffer (BUF1 to BUFn).The power control module PCM controls each state of each subcircuit.

The power arbiter ARBIT controls the state of each subcircuit inaccordance with the above subcircuit scheduling with reference to thevalue in the power table PWRTAB provided in each of the power controlmodules PCM1 to PCMn. Each of the power control modules PCM1 to PCMncontrols the power of each of the subcircuits CKT1 to CKTn, while thepower arbiter ARBIT adjusts the power consumption among the subcircuitsCKT1 to CKTn. The processing required for the subcircuit scheduling canbe dispersed among hierarchical layers, whereby each hierarchical layercan be designed more easily.

The circuit for limiting the state transition frequency of eachsubcircuit CKT can be realized by a power control module (one of PCM1 toPCMn). In another example, when a subcircuit CKT is not accessed for acertain time, the power control module PCM corresponding to thesubcircuit changes the state of the subcircuit so as to reduce the powerconsumption independently of the power arbiter and communicates the newstate and the power consumption to the power arbiter. Consequently, itis possible to realize subcircuit scheduling that can reduce the powerconsumption of the chip CHP1 effectively without applying an excessiveprocessing load to the power arbiter ARBIT.

Tenth Embodiment

FIG. 10 shows a flowchart for designing a semiconductor device thatrealizes power controlling for the chip of the present invention. Alibrary LG_LIB1 stores circuits for realizing the functions ofsubcircuits CKT. Each of the subcircuits CKT is not provided with apower control module PCM shown in the embodiment in FIG. 9. The libraryPCM_LIB1 stores the power control module PCM corresponding to eachsubcircuit CKT in the LG_LIB1. The library LG_LIB2 is also a library ofsubcircuits CKT, but each subcircuit CKT stored in the library LG_LIB2is already provided with a power control module PCM. The library MC_LIBstores the main circuit MCKT shown in the first embodiment in FIG. 1.

The four libraries (LG_LIB1, PCM_LIB1, LG_LIB2, and MC_LIB) and the chipkernel CHPKNL are stored as data in which the function of eachsubcircuit is described by a language such as the HDL (HardwareDescription Language) A logic synthesizing cell library CELL_LIB storesinformation (e.g., each cell type time delay information) of each celltype (e.g., cells of such logical gates or composite logical gates asAND, OR) used for synthesizing logics. The designer preferably createsthe logical specification RTL (Register Transfer Level), RTL being oneexample and the invention not limited thereto, related to the whole chipand synthesizes the logics (LOG SYN) of the net lists NETLST from thelogical specifications RTL, as well as from the circuit data and thecell information stored in the library. The net list NETLST is then laidout (LAY).

The above-mentioned design flow makes it possible to apply the powercontrol method of the present invention to any subcircuit (stored in thelibrary LG_LIB1) when the power control module PCM is added to thesubcircuit, although it may otherwise be difficult to apply the powercontrol method to such a subcircuit with no modification. This makes itdifficult to use many IN (Intellectual Property: a circuit block usedfor a collection of computing functions, signal control functions, andother functions that is provided on an IC) supplied from “IP providers”on a chip to be designed, whereby the chip may be designed moreefficiently.

The power control module PCM is preferably created for each subcircuitseparately. Consequently, the PCM is designed on the basis of thespecifications of the interface (hereafter, “Power Scheduling Interface”or “PSI”) between a power arbiter ARBIT and a power control module PCM.The PSI includes a protocol used for commands from the power arbiterARBIT and the returned protocol of the power control module in responseto those commands.

In the same way, the designer who is to design the logicalspecifications RTL can understand the specifications of the interfacebetween the power control module PCM and each subcircuit CKT and designeach subcircuit controlled by the request signal REQS and theacknowledge signal ACKS (Hereafter, the interface is called “PowerManaging Interface” or PMI”). The PMI includes a protocol used for therequest signal from the main circuit MCKT or subcircuit block CKT andthe acknowledge signal REQS from the chip kernel CHPKNL.

According to the interface specifications PMI and PSI, the powercontrolling of the present invention can be realized more easily withuse of existing circuit block designs.

Eleventh Embodiment

FIG. 11 shows an embodiment of a chip (CHP3) for which the power controlmethod of the present invention is employed. In FIG. 11, an on-chip busSBUS in the chip (CHP3) is used to transfer signals. The SBUS isconnected to a microprocessor (Central Processing Unit) CPU, a LongInstruction Word type microprocessor VLIW, a digital signal processorDSP, a graphic processor GP, an MPEG (Moving Picture Experts Group)signal processor circuit MPEG, a bus control circuit BSC, a chip powercontrol circuit PMU, a USB (Universal Serial Bus) interface circuit USB,an IrDA (Infrared Data Association) infrared beam communicationinterface circuit IrDA, an IEEE1394 interface circuit IEEE1394, a PCI(Peripheral Component Interconnect) interface circuit PCI, and a memoryMEM. The EXTBUS is an external bus and is connected to the on-chip SBUSvia the bus controller BSC. The CHP3 processes data with use of suchdedicated circuits as CPU, VLIW, DSP, GP, MPEG, as well as the memoryMEM so as to send/receive. data to/from external devices with use ofUSB, IrDA, IEEE1394, PCI, and BSC. However, these particular listedcircuit blocks are merely exemplary. They are selected and mountedappropriately for the desired functionality of chip CHP3. The powercontrol bus PBUS is used for the power control method of the presentinvention.

The power of the chip CHP3 is preferably controlled as follows. The chippower control circuit PMU controls the power state of the whole CHIP3according to instructions (e.g., interrupt) from outside the chip CHP3(e.g., EXTBUS) or command strings (e.g., standby command) executed bythe CPU and others. For example, the PMU controls the whole chip CHP3 soas to increase/decrease the operational speed or make the chip CHP3stand by and rest (hereafter, each whole chip state is referred to as a“chip states”). The chip power control circuit PMU controls the chipkernel CHPKNL so as to set the chip CHP3 in various states as describedabove. Although the control of the chip kernel CHPKNL of the chip powercontrol circuit PMU is not limited specifically, the chip kernel CHPKNLcan also be controlled by changing the Pmax value of the chip kernelCHPKNL according to each chip state. This chip kernel CHPKNL is alsoused to control the power of every circuit module in accordance with themethod of the present invention. The chip kernel CHPKNL may be anindependent circuit block, as shown in FIG. 11, and it may be realizedto have some functions of a circuit block (e.g., CPU).

Generally, the power consumption of a dedicated circuit is less thanthat of a general circuit. This is because, when compared with a generalcircuit, such a dedicated circuit has less redundant functionalcircuits. For example, power consumption, when a dedicated circuit isused for an MPEG processing, is less than when a general circuit is usedfor that. Because the chip CHP3 of the present invention is enabled forvirtual integration as described above, many dedicated circuits can beintegrated on the chip CHP3 just like in the embodiment shown in FIG.11. Thus, the use of dedicated circuits, not general circuits, will makeit possible to reduce the chip power consumption more significantly.

Twelfth Embodiment

The chip of the present invention may reduce the variation of the powerconsumption more than any of the conventional chips. None of theconventional chips gives consideration to the total power consumption ofthe chip for controlling the power of each subcircuit. This is why thepeak power value (thermal design power) usually is several times greaterthan the average power. On the contrary, the chip of the presentinvention preferably enables its total power consumption to be limitedwithin a preset maximum power consumption Pmax, whereby the use of anysubcircuit that might exceed the Pmax value is delayed until a latertime. The use of the subcircuit preferably is only enabled after amargin is generated in the power consumption of the chip, so that thePmax value is not exceeded in accessing the subcircuit. Therefore, thepower consumption of a conventional chip is reduced so as to increasethe capacity of the power processing with the reduced power consumption.The maximum power consumption of the chip is lower than the peak powerof the conventional chip, so that it can become closer to the averagepower value. Consequently, the time variation (di/dt) of the powerconsumption of the chip is eased. This time variation di/dt of the powerconsumption generates a voltage time variation dV/dt represented byLdi/dt (L: power line inductance of the chip). The present invention canthus have an effect that the chip voltage variation can be suppressedlower than any of the conventional chips.

As described above, the maximum power consumption of the chip can bechanged in the fourth embodiment. In this embodiment, a description willbe made for a method for changing the Pmax value so as to reduce thevoltage variation (Ldi/dt) FIG. 12 shows an embodiment for controllingthe maximum power Pmax in three steps according to, for example, theload of the chip.

The state 1 of the chip (ST1) means a state in which the chip is notpowered or the subject circuit stands by or stops. For example, thestate assumes Pmax=0. The state 2 of the chip (ST2) means a state inwhich the processing load of the chip is small, so that no problemarises from a processing delay even when the Pmax value is comparativelylow. For example, the state assumes Pmax=5. The state 3 of the chipmeans a state in which the processing load of the chip is large, so thata higher Pmax value must be set so as to suppress a processing delay.For example, the state assumes Pmax=10. This embodiment enables the Pmaxvalue to be changed step by step during each state transition of thechip. For example, in the case where k subcircuit blocks are activatedat a time when the state is transferred from state 1 to state 2 in allthe subcircuits at a time, the number of subcircuit blocks to beactivated at a time can be suppressed lower than the k value when in thestep-by-step controlling. As a result, the voltage variation to becaused by a current variation can be reduced.

Thirteenth Embodiment

FIG. 13 shows an example of the dependency of the average power AVEP andthe task execution time EXET on Pmax with respect to the chip of thepresent invention.

The dotted line denotes the average power and the solid line denotes theexecution time. Note that, however, no leakage current of the transistoris taken into consideration in this average power shown in FIG. 13.According to the level of dependency on the Pmax value, the graph isroughly divided into two areas (area A and area B). In area A, thereappears almost no change in both average power AVEP and execution timeEXET even when the Pmax is changed. On the other hand, as the Pmax valueis reduced, the average power AVEP is reduced and the execution timeEXET is increased in area B.

The state in the area A is a state in which no execution time delayoccurs in the whole task even when the access to some subcircuits isdelayed until a later time, since the access to the delayed subcircuitsis enabled together with other subcircuits to be accessed at that timewhen the power consumption has a margin. On the other hand, the area Bis a state in which the subcircuits are accessed within a power close tothe Pmax and the access to some subcircuits that is left until a latertime affects the execution time of the whole task to a certain level.The Pmax, which becomes a boundary between areas A and B takes a value(10 W in the example shown in FIG. 13) around the average powerAVEP(.infin.) when the chip maximum power of the chip is .infin.. Theexecution time of the whole task is extended unavoidably, whereby thelimit of the maximum power Pmax of the chip causes the power consumptionto be lowered directly when the Pmax value is set to AVEP(.infin.) orless.

As described above, the energy consumption by a whole task processingcalculated from the product between the average power AVEP and theexecution time EXET does not depend on the Pmax. The AVEP is calculatedby excluding the leakage current and the power consumption used forpower management.

On the other hand, a leakage current is a current flowing in anoff-state transistor. It is generated independently of any taskprocessing. However, as described with reference to FIG. 5 in the firstembodiment, each subcircuit in the present invention can be configuredso as to be transferred to a power-saving mode according to the statetransition frequency. When this configuration is taken, the taskprocessing time can be extended by reducing the Pmax value and eachinactive subcircuit can go into the power-saving mode that suppressesthe leakage current. Thus, the power consumption caused by the leakagecurrent can also be reduced. Consequently, when the leakage current istaken into consideration and the Pmax is set low, the task processingtime is extended and the energy consumption by the whole task processingis reduced.

Where a state identical to that in the twelfth embodiment is set, thePmax is determined with respect to the average power AVEP(.infin.) whenthe maximum power is (.infin.). Consequently, it is the average powerwhen the task processing control is done according to the powerconsumption of the whole chip. This AVEP(.infin.) size is decided mainlyby the chip system configuration and it is hot changed much by thecontent of the subject task.

In the chip state 2 (ST2), an emphasis is put on the chip operation atlower power consumption. The Pmax(ST2) value takes a value in the areaB; for example, it assumes Pmax=5 W. In the chip state 3 (ST3), anemphasis is put on the operation of the chip at lower power consumptionand at the minimum reduction of the operation speed. The Pmax(ST3) takesa value in the area A; for example, it assumes Pmax=10 W. The influenceof a leakage current on an energy consumption can be reduced bycontrolling the Pmax so as to make the absolute value of(Pmax(ST3)-AVEP(.infin.)) smaller than the absolute value of(Pmax(ST2)-AVEP(.infin.)).

As described above, while the present invention has been described indetail with reference to some preferred embodiments, it is to beunderstood that modifications will be apparent to those skilled in theart without departing from the spirit of the invention. For example, thespecific structure and layout of the circuit shown in FIG. 1 can bevaried freely. The present invention can thus apply to a wide variety ofchips or systems that employ the chips in each of which the powerconsumption exceeds the maximum power when all the circuits integratedon the chip are powered or activated.

While a description has been made for a method for controlling the chippower consumption at a resource, the resources to be controlled are notlimited only to the chip power consumption. For example, it is alsopossible to control transistors, gates, or wirings integrated on thechip as such resources when the chip is configured so as to bere-configurable (a chip configured so as to use one and the sametransistor or gate as a part for realizing a different function bychanging the wiring structure electrically or physically after thefabrication).

According to the present invention, therefore, it is possible tointegrate many low threshold voltage MOS transistors and thin gate oxideMOS transistors on one single chip while it has been impossibleconventionally to integrate such many MOS transistors due to the powerlimitation of the chip.

The foregoing invention has been described in terms of preferredembodiments. However, those skilled, in the art will recognize that manyvariations of such embodiments exist. Such variations are intended to bewithin the scope of the present invention and the appended claims.

Nothing in the above description is meant to limit the present inventionto any specific materials, geometry, or orientation of elements. Manypart/orientation substitutions are contemplated within the scope of thepresent invention and will be apparent to those skilled in the art. Theembodiments described herein were presented by way of example only andshould not be used to limit the scope of the invention.

Although the invention has been described in terms of particularembodiments in an application, one of ordinary skill in the art, inlight of the teachings herein, can generate additional embodiments andmodifications without departing from the spirit of, or exceeding thescope of, the claimed invention. Accordingly, it is understood that thedrawings and the descriptions herein are proffered by way of exampleonly to facilitate comprehension of the invention and should not beconstrued to limit the scope thereof.

1. A semiconductor integrated circuit device comprising: a plurality offirst circuit blocks, each of the plurality of first circuit blockshaving-operating states which include at least a first state and asecond state and a power management block including a memory whichstores a maximum chip power value that is referred when the operatingstate for each of the plurality of first circuit blocks is determined,wherein each of the plurality of first circuit blocks in the first stateis activated by higher operational frequency than each of the pluralityof the first circuit blocks in the second state, wherein each of theplurality of first circuit blocks in the first state is activated bylarger power consumption than each of the plurality of the first circuitblocks in the second state, wherein a sum of power consumptions of theplurality of the first circuit block is lower than the maximum chippower value if all of the plurality of first circuit blocks are in thefirst state and higher than the maximum chip power value if all of theplurality of first circuit blocks are in the second state, and whereinthe power management permits an operating mode that at least one of theplurality of the first circuit blocks operates in the second state.